Synapse32

A 32-bit 5-stage pipelined RISC-V CPU

verilog fpga vivado rtl design
github

Synapse-32 is a 32-bit RISC-V CPU core written in Verilog, supporting RV32I instructions, along with Zicsr and Zifencei extensions.

Processor Architecture

5-Stage Pipeline

This processor implements a classic 5-stage RISC pipeline:

  1. IF (Instruction Fetch): Fetches the next instruction from instruction memory and updates the Program Counter (PC)

  2. ID (Instruction Decode): Decodes the instruction, reads values from register file, and generates immediate values and control signals

  3. EX (Execute): Performs ALU operations, calculates branch/jump addresses, and makes branch decisions

  4. MEM (Memory Access): Performs memory reads and writes, handles load and store instructions

  5. WB (Write Back): Writes results back to the register file and selects appropriate data source (ALU or memory)

Pipeline Hazard Handling

The CPU implements several techniques to handle pipeline hazards:

Data Forwarding

  • Resolves Read-After-Write (RAW) hazards
  • Forwards data from EX/MEM and MEM/WB stages to the EX stage
  • Avoids pipeline stalls in most cases

Load-Use Hazard Detection

  • Detects when an instruction immediately needs data from a preceding load
  • Inserts pipeline stalls when necessary

Control Hazard Management

  • Handles branch and jump instructions
  • Flushes the pipeline when branches are taken
  • Supports efficient control flow

Key Features

  • RV32I Base Integer Instruction Set: Complete implementation of the 32-bit RISC-V base instruction set
  • Zicsr Extension: Control and Status Register (CSR) instructions
  • Zifencei Extension: Instruction-Fetch Fence support
  • Optimized Pipeline: Efficient hazard handling with forwarding and stall logic
  • Tested and Verified: Comprehensive regression test suite using Cocotb