A 32-bit 5-stage pipelined RISC-V CPU
verilog fpga vivado rtl design
नमस्कार
This is my portfolio where you will find my projects and the things i write. Just a guy interested in tech finding his way into the world.
Feel free to look around.
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carpe diem
/ˌkɑːrpeɪ ˈdiːem/ • Latin
used to urge someone to make the most of the present time and give little thought to the future.
"seize the day"
